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The Latest Breaking News from Kevin Zhang

Broadcom unveils gigantic 3.5D XDSiP platform for AI XPUs — 6000mm² of stacked silicon with 12 HBM modules

Broadcom's 3.5D XDSiP platform for high-performance processors uses TSMC's CoWoS and other packaging technologies to build a system-in-packages comprising 6000mm² of 3D-stacked silicon with 12 HBM modules.

Tom’s Hardware

10 Years Later, the Publisher of the World’s Weirdest Video Games Is Doubling Down

10 Years Later, the Publisher of the World’s Weirdest Video Games Is Doubling Down

Ten years later, the co-founders of Serenity Forge sit down to talk about Doki Doki Literature Club, Roman Sands Re:Build, and others.

TSMC VP says 'I don’t care if Moore’s Law is alive or dead' if technology keeps scaling — 3D chip packaging fuels continued advances

TSMC VP says 'I don’t care if Moore’s Law is alive or dead' if technology keeps scaling — 3D chip packaging fuels continued advances

TSMC's Kevin Zhang states that while Moore's Law's traditional focus on transistor density may be less relevant, TSMC's continual advancements in technology scaling and 2.5D and 3D integration make it more than alive.

Tom’s Hardware

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TSMC Offers a Peek at 'Global Gigafab' Process Replication Program

At its European Technology Symposium last week TSMC revealed some of the details about its Global Gigafab Manufacturing program, the company's strategy to replicate its manufacturing processes across its multiple gigafab sites. The need for large-scale multi-national fabs to have a process in place to replicate their facilities is well-documented…

TSMC to Expand Specialty Capacity by 50%, Introduce 4nm N4e Low-Power Node

With all the new fabs being built in Germany and Japan, as well as the expansion of production capacity in China, TSMC is planning to extend its production capacity for specialty technologies by 50% by 2027. As disclosed by the company during its European Technology Symposium this week, TSMC expects…

TSMC's System-on-Wafer Platform Goes 3D: CoW-SoW Stacks Up the Chips

TSMC has been offering its System-on-Wafer integration technology, InFO-SoW, since 2020. For now, only Cerebras and Tesla have developed wafer scale processor designs using it, as while they have fantastic performance and power efficiency, wafer-scale processors are extremely complex to develop and produce. But TSMC believes that not only will…

TSMC says it doesn't need High-NA EUV chipmaking tools for 1.6nm-class node, but Intel has championed the tech

TSMC says it will not need a high-NA litho tool for its A16 technology but will keep exploring it for A16 and beyond.

Tom’s Hardware

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TSMC Preps Cheaper 4nm N4C Process For 2025, Aiming For 8.5% Cost Reduction

TSMC Preps Cheaper 4nm N4C Process For 2025, Aiming For 8.5% Cost Reduction

While the bulk of attention on TSMC is aimed at its leading-edge nodes, such as N3E and N2, loads of chips will continue to be made using more mature and proven process technologies for years to come. Which is why TSMC has continued to refine its existing nodes, including its…

SK Hynix and TSMC Team Up for HBM4 Development

SK Hynix and TSMC Team Up for HBM4 Development

SK hynix and TSMC announced early on Friday that they had signed a memorandum of understanding to collaborate on developing the next-generation HBM4 memory and advanced packaging technology. The initiative is designed to speed up the adoption of HBM4 memory and solidify SK hynix's and TSMC's leading positions in high-bandwidth…

Marvell's 2nm IP Platform Enables Custom Silicon for Datacenters

Marvell's 2nm IP Platform Enables Custom Silicon for Datacenters

Marvell this week introduced its new IP technology platform specifically tailored for custom chips for accelerated infrastructure made on TSMC's 2nm-class process technologies (possibly including N2 and N2P). The platform includes technologies essential for developing cloud-optimized accelerators, Ethernet switches, and digital signal processors. "The 2nm platform will enable Marvell to…

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