One of AMD's EPYC processors' competitive advantages (except those in AM5 packaging, of course) has always been their set of 128 PCIe lanes, which allow the installation of plenty of accelerators and/or high-end storage devices. But Intel is looking to give AMD's CPUs a fight with its Xeon 6 R1S processor with 136 PCIe lanes, reports ServeTheHome. There is a catch, though: the CPU is designed for single-socket systems only.
Intel's Xeon 6 R1S is a part of Intel's Xeon 6700-series Granite Rapids family, featuring high-performance CPU cores that are targeted at users who need ample PCIe connectivity but do not require the highest core counts found in Xeon 6900-series CPUs. The processor features up to 136 PCIe Gen5 lanes, making it ideal for high-end storage applications. Still, it could also be used for multiple accelerators or special-purpose add-in-board applications. Additionally, it supports up to 64 lanes of CXL 2.0 for applications like accelerators or memory expanders. The processor will have eight-channel DDR5 memory channels supporting DDR5-6400 memory or faster MCRDIMMs. Total memory capacity is unknown.
Since we are dealing with a Granite Rapids-based Xeon 6700-series CPU, expect this one to feature up to 86 high-performance cores, though ServeTheHome believes the actual number will be '~80.' Given that this is a processor for a single-socket machine in an LGA4710 packaging, do not expect this one to power AI or HPC servers that tend to use two CPUs. However, this promises to be a competitive offering for communications, storage, edge, and various special-purpose machines, even with 'only' up to 86 cores but with 136 PCIe lanes.
Considering Intel's Xeon R1S's possible positioning, expect it to compete against AMD's EPYC 8004-series CPUs. It looks like Intel is set to outshine the rival in this area, as the EPYC 8004-series has 64 cores and 96 PCIe Gen5 lanes.
While Intel has disclosed quite a lot about the Xeon 6 R1S, the company has not yet revealed what, if any, Accelerator Engines for encryption, compression, and data movement (or other?) will be included in these processors. If enabled, the R1S could become a versatile solution for various applications.
