Loongson has posted the first Linux patches to enable support for its next generation 3A6000-series processors, reports Phoronix. The company expects its upcoming LoongArch-based CPUs AMD's Zen 3 in instruction per clock (IPC), which will enable Loongson to challenge leading processor manufacturers.
Loongson shared details about the progress of its 3A6000-series CPU development last November when it revealed that the design phase of the project had been concluded and that samples of the processors would be available in the first half of 2023.
Now, the company's engineers posted patches enabling the 3A6000's new memory management unit (MMU) or page table walker (PTW) that can handle address translation exceptions (like TLBI, TLBL, TLBS, TLBM) directly in the hardware, boosting performance. The CPU will only require software handling in situations like page faults.
Another feature enabled by another patch for Loongson's 3A6000's processors is moving away from full completion barrier (dbar 0) hint to a set of more fine-tuned hints for different memory barriers, which can improve performance.
CPU enablement in Linux is an important milestone for any processor development cycle, since it signals that development is proceeding. Enablement alone does not necessarily mean that the new chip is about to be taped out, or is progressing rapidly, but at least it means that its designers are confident enough about its success.
Matching IPC performance of AMD's Zen 3 microarchitecture or Intel's Tiger Lake microarchitecture is a big deal for Loongson, whose current CPUs are considerably slower than processors from the leading suppliers. Meanwhile, it should be noted that IPC alone does not necessarily mean that Loongson's 2nd Generation CPUs that rely on its LoongArch microarchitecture will be as fast as AMD's Ryzen 5000-series or Intel's 11th generation Core processors. Clock speed and other aspects of the platform will also play a role.
