It's no secret that Intel is preparing its 14th Generation Meteor Lake to rival the best CPUs. The chipmaker has already shared some feature sets for the upcoming Foveros-packaged chips. However, a new Linux patch implies that Meteor Lake will sport an L4 cache, which is infrequently used on processors.
The description from the Linux patch reads: "On MTL, GT can no longer allocate on LLC - only the CPU can. This, along with addition of support for ADM/L4 cache calls a MOCS/PAT table update."
The patch didn't specify what "ADM" stands for. It could just be a fancy marketing name for the L4 cache. The code didn't expose the size of the ADM, either. Historically, Intel has used 64MB or 128MB for the eDRAM for Haswell through Coffee Lake. During its Hot Chips 34 presentation, Intel shared the schematics of the Meteor Lake chip, which comprises four different tiles: CPU tile, SoC tile, IO extender tile, and graphics tile. The quartet sits atop a large base tile that acts as an interposer.
Intel's first implementation of the eDRAM (embedded DRAM) was with Haswell and served as an L4 cache for the CPU and iGPU. The chipmaker would continue this practice until Coffee Lake. However, only a few selected desktop and mobile chips leveraged eDRAM over its short usage span. Broadwell was the most prominent architecture to feature eDRAM. Chipmakers typically shun the L4 cache from their designs because it's slower.
The cache hierarchy spans from L1 to L4, but most processors stop at L3 because speed decreases as you go down the ranks. Lower-level caches are larger and thus increasing the chances of a cache hit. The main problem is that accessing the lower caches, such as L3 or even L4 takes longer. So outside of feeding the integrated graphics, there are very few scenarios where the L4 cache helps in system performance. However, according to some Linux patches that Coelacanth's Dream has unearthed, the L4 cache could make a comeback with Meteor Lake.
The big question is where Intel will place the ADM/L4 cache. It's possible that Meteor Lake's base tile may house the L4 cache. For example, Ponte Vecchio's base tile carries 144MB of L2 cache, so there's precedent for it. Alternatively, the L4 cache may reside inside the SoC tile and would certainly explain its large landscape.
Another exciting discovery is that Intel has seemingly blocked Meteor Lake's iGPU from accessing the LLC (last level cache). As per the developer notes from the Linux patch, "On MTL, GT is no longer allocated on LLC, set has_llc=0."
LLC corresponds to the highest-numbered cache on the processor where it has to hit the memory. The L3 is typically the LLC in most modern processors, shared among the CPU cores and iGPU. For example, Intel's existing 13th Generation Raptor Lake chips arrive with up to 36MB of L3 cache, representing a 20% improvement over the last 12th Generation Alder Lake parts. However, the Linux patch states that only the CPU cores on Meteor Lake can tap into the LLC. The design is similar to AMD's Ryzen APUs, where CPU cores and iGPU don't share the same cache.
A 12-core Meteor Lake processor recently emerged on a benchmark website. Sadly, the chip's misreported clock speeds and results couldn't provide a concrete picture of how much performance uplift we can expect over Raptor Lake. So it's still unclear if Meteor Lake will stay mobile only, like Ice Lake or Tiger Lake, or whether it'll come to the desktop. On the other hand, there have been months-long rumors about a potential Raptor Lake Refresh, so the latter doesn't sound unlikely. An alleged Intel document only confirms that the marketing name for Meteor Lake is 14th Generation Core but doesn't exactly dispel the rumors.
Meteor Lake should hit the retail market in the second half of this year. After that, the 7nm chips will go up against some stiff competition from AMD, including Dragon Range (Zen 4 + RDNA 2), Phoenix (Zen 4 + RDNA 3), and the refreshed Rembrandt-R and Barcelo-R chips.
